1. Field of the Invention
The present invention relates to an element isolation method for semiconductor devices, and more particularly to a shallow trench isolation (STI) method using a shallow trench according to the design rule for highly integrated semiconductor devices.
2. Description of the Related Art
Generally, the STI process is known as an element isolation technique, which is currently regared as an efficient process for semiconductor devices, in that it advantageously involves no bird's beak effect while providing a vertical element isolation capable of completely isolating elements from one another.
In conventional STI processes, however, where misaligned metal contacts are formed, the misaligned metal contacts may be short-circuited with wells in spite of a plug ion implantation, thereby resulting in a failure.
This is because a vertical STI structure is formed in accordance with conventional STI processes. Where such a vertical STI structure is formed, a possible misalignment of metal contacts results in the absence of doping of desired ions on the surface of a polysilicon substrate at regions where the metal contacts have vertical edges laterally spaced from the polysilicon surface in a plug implantation process. That is, although an implantation of N.sup.+ ions is conducted for a structure in which metal contacts are misaligned, as shown in FIG. 1, portions of the structure indicated by circles D in FIG. 1 are not doped with N.sup.+ ions so that those metal contacts may be short-circuited with P-wells.
In order to avoid such a phenomenon, therefore, it is necessary to obtain an increased metal contact margin in the STI process.